1. Technical Field
The present invention relates to an architecture for data processing in general, and in particular to a peripheral component interconnect architecture within a data-processing system. Still more particularly, the present invention relates to an enhanced peripheral component interconnect architecture having hot-plugging capability for a data-processing system.
2. Description of the Prior Art
A computer system or data-processing system typically includes a system bus. Attached to the system bus are various devices that may communicate locally with each other over the system bus. For example, a typical computer system includes a system bus to which a central processing unit (CPU) is attached and over which the CPU communicates directly with a system memory that is also attached to the system bus.
In addition, the computer system may include a local bus for connecting certain highly integrated peripheral components on the same bus as the CPU. One such local bus is known as the Peripheral Component Interconnect (PCI) bus. Under the PCI local bus standard, peripheral components can directly connect to a PCI local bus without the need for "glue" logic. Thus, PCI provides a bus standard on which high-performance peripheral devices, such as graphics displaying devices and motion video displaying devices, can be coupled to the CPU, thereby permitting these high-performance peripheral devices to avoid the general access latency and the bandwidth constraints that would have occurred if these peripheral devices were connected to a standard peripheral bus.
PCI local bus is a high performance, 32-bit or 64-bit bus with multiplexed address and data lines. Any PCI component and add-in card interface is processor independent, enabling an efficient transition to future processor generations and usage with multiple processor architectures. Processor independence also allows the PCI local bus to be optimized for I/O functions, enables concurrent operation of the local bus with the processor/memory subsystem, and accommodates multiple high performance peripheral devices. In addition, a transparent 64-bit extension of the 32-bit data and address buses under the PCI local bus allows the bus bandwidth to be doubled and offers forward and backward compatibility of 32-bit and 64-bit PCI local bus peripherals.
Most computer buses are generally not designed to handle any unexpected removal of peripheral devices from the bus itself. Suffice to say, inserting or removing an adapter card from an adapter slot that is attached to a computer bus without following the proper sequence may lead to unpredictable results, including data corruption, abnormal termination of operating system, or damage to adapter card or platform hardware.
There is a provision for hot-plugging capability under the PCI local bus, and the hot-plugging standard for PCI local bus is defined under the PCI Hot-Plug Specification, Revision 0.9, promulgated by the PCI Special Interest Group, which is hereby incorporated by reference. While the PCI hot-plug standard is generally defined in the above-mentioned publication, the detailed implementation is not specified. The present disclosure describes the electronics and service indicators of an enhanced PCI architecture that are necessary to enable such hot-plugging capability.